1. Field of the Invention
The present invention relates to magnetic tunnel junction structures suitable for use in magnetic random access memory (MRAM) cells and methods of fabricating such structures, particularly with respect to the bottom electrode of such structures.
2. Description of the Related Art
Semiconductor memory devices for storing data can generally be categorized as either volatile memory devices or nonvolatile memory devices. Volatile memory devices are those that lose the stored data when their power supplies are interrupted while nonvolatile memory devices are those that retain the stored data even when their power supplies are interrupted. Accordingly, nonvolatile memory devices including flash, static random access memory (SRAM), ferroelectric random access memory (FeRAM) and magnetic random access memory (MRAM) devices have been used in memory cards, mobile telecommunication systems and other electronic devices for maintaining stored data while reducing power consumption.
A conventional MRAM device comprises a plurality of memory cells employing magnetic tunnel junction (MTJ) structures. FIG. 1 provides a cross-sectional view of a conventional MRAM cell having such a MTJ structure.
Referring to FIG. 1, the conventional MRAM cell comprises a MTJ structure 16 including a bottom electrode 1, a seeding layer 3, a pinning layer pattern 5, a pinned layer pattern 7, a tunneling layer pattern 9, a free layer pattern 11, a capping layer pattern 13 and a top electrode 15, which are sequentially stacked. A digit line 17 is disposed under and electrically insulated from the bottom electrode 1. A bit line 19 is positioned over and in electrical contact with the top electrode 15 and is arranged generally perpendicular to the digit line 17.
In the conventional MRAM cell, the bottom electrode 1 may be a stacked structure including both a titanium layer and a titanium nitride layer. The titanium layer is typically used as a wetting layer for improving the adhesion between the titanium nitride layer and the insulating layer under the titanium layer. The seeding layer 3 is typically a NiFe layer and is used for controlling the crystalline orientation of the pinning layer pattern 5. The pinned layer pattern 7 and the free layer pattern 11 are formed of an anti-ferromagnetic layer and a ferromagnetic layer, respectively. During operation of the MRAM cell, the pinned layer pattern 7 acts as a magnetic reference layer while the free layer pattern 11 acts as a magnetically changeable layer.
The pinning layer pattern 5 determines the magnetization direction of the pinned layer pattern 7, but does not exert a similar influence on the magnetization direction of the free layer pattern 11. The free layer pattern 11 may, instead, be selectively magnetized by current flowing through the digit line 17 during a write operation. When the magnetization direction of the free layer pattern 11 is parallel or substantially parallel to that of the pinned layer pattern 7, the tunneling layer pattern 9 will exhibit a relatively low resistance value. However, when the magnetization direction of the free layer pattern 11 is antiparallel or substantially antiparallel to that of the pinned layer pattern 7, the tunneling layer pattern 9 will exhibit a relatively high resistance value. Accordingly, the MRAM cell may be read by applying a read voltage to the bit line 19 and sensing the bit line current that flows through the tunneling layer pattern 9 and the bottom electrode 1.
Aluminum oxide layer has been widely used in formation of the tunneling layer pattern 9. When aluminum oxide is used in this manner, the layer thickness is generally maintained at 30 Å or less in order to obtain better tunneling characteristics. The tunneling layer should also have a smooth surface without any pinholes or other defects to provide improved reliability. The tunneling layer should also have a generally uniform thickness across the entire wafer in order to produce MRAM devices having consistent performance. Because the magnetic resistance of an aluminum oxide tunneling layer is exponentially proportional to its thickness, variations in the layer thickness produce even wider and undesired variations in the magnetic resistance.
A bottom electrode 1 formed from a titanium nitride layer as described above tends to exhibit poor surface morphology with a high degree of surface roughness. When the bottom electrode exhibits a poor surface morphology, the aluminum oxide layer formed above also tends to exhibit a similar poor surface morphology, i.e., a high surface roughness, as a result of the condition of the titanium nitride layer. Further, the pinning layer pattern 5 and the pinned layer pattern 7 formed over the bottom electrode may also tend to have surfaces that exhibit a similar degree of surface roughness. When the pinning layer pattern has a rough surface, the net magnetization of the pinned layer pattern 7 will be reduced and tend to degrade the hysteresis loop characteristics of the resulting MTJ structure.